CNN Accelerator

Overview

For EE272 (Design Projects in VLSI), I designed a hardware CNN accelerator built around a 16x16 systolic array optimized for ResNet-18 inference. The accelerator was implemented using Catapult High-Level Synthesis (HLS), translating a high-level dataflow description into optimized RTL.

The systolic array architecture maximizes data reuse and throughput for the matrix-multiplication-heavy convolution operations that dominate ResNet-18, while HLS enabled rapid design-space exploration of the power, performance, and area (PPA) trade-offs.