PPA Optimized Triangle Rasterizer

Overview

For EE271 (Introduction to VLSI Systems), I designed and optimized a triangle rasterizer in Verilog, achieving a top 10% figure of merit (FoM) in the graduate-level course.

The optimization spanned multiple EDA tools and Verilog, applying a range of techniques to improve power, performance, and area (PPA):

• Clock gating to reduce dynamic power
• Retiming to balance pipeline stages and improve timing
• Pipelining to increase throughput
• Bubble smashing to eliminate stalls and improve effective throughput